about brains and silicon wafers

Please read this first paragraph and let it settle:

At the core of the BrainScaleS wafer-scale hardware system (see Figure 90) is an uncut wafer built from mixed-signal ASICs [1], named High Input Count Analog Neural Network chips (HICANNs), which provide a highly configurable substrate that physically emulates adaptively spiking neurons and dynamic synapses (Schemmel et al. (2010)Schemmel et al. (2008)).

I’ve highlighted in bold the portion that I want you to think about once more. We are not talking about chips, dies or cut-up wafers.

We are talking about real-size, huge, fully developed wafers filled with logic. For the sole purpose of brain scale neural network research and development…

The Neuromorphic Computing Platform allows neuroscientists and engineers to perform experiments with configurable neuromorphic computing systems. The platform provides two complementary, large-scale neuromorphic systems built in custom hardware at locations in Heidelberg, Germany (the “BrainScaleS” system, also known as the “physical model” or PM system) and Manchester, United Kingdom (the “SpiNNaker” system, also known as the “many core” or MC system). Both systems enable energy-efficient, large-scale neuronal network simulations with simplified spiking neuron models. The BrainScaleS system is based on physical (analogue) emulations of neuron models and offers highly accelerated operation (104 x real time). The SpiNNaker system is based on a digital many-core architecture and provides real-time operation.

https://electronicvisions.github.io/hbp-sp9-guidebook/index.html

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